Previous Blogs

March 30, 2023
Amazon Enables Sidewalk Network for IoT Applications

March 16, 2023
Microsoft 365 Copilot Enables the Digital Assistants We’ve Always Wanted

March 14, 2023
Google Unveils Generative AI Tools for Workspace and GCP

March 9, 2023
Lenovo Revs Desktop Workstations with Aston Martin

March 1, 2023
MWC Analysis: The Computerized, Cloudified 5G Network is Getting Real

February 23, 2023
Early MWC News Shows Renewed Emphasis on 5G Infrastructure

February 1, 2023
Samsung Looking to Impact the PC Market

January 18, 2023
The Surprise Winner for Generative AI

January 5, 2023
AI To Go Mainstream in 2023

2022 Blogs

2021 Blogs

2020 Blogs

2019 Blogs

2018 Blogs

2017 Blogs

2016 Blogs

2015 Blogs

2014 Blogs

2013 Blogs


















TECHnalysis Research Blog

April 20, 2023
Latest Cadence Tools Bring Generative AI to Chip and System Design

By Bob O'Donnell

One of the most intriguing aspects about the generative AI trend is how many different—and unexpected—places the technology is already starting to make an impact. At the recent CadenceLive event, computational software and EDA (electronic design automation) industry stalwart Cadence Design Systems took that concept even further and highlighted how it is bringing aspects of generative AI to new versions of its semiconductor chip design and PCB (printed circuit board) design tools.

The latest version of the company’s Virtuoso application—now dubbed Virtuoso Studio—brings new capabilities to analog, RF (radio frequency) and custom silicon designs that leverage generative AI principles. Among several other enhancements, Virtuoso Studio incorporates the ability to move existing chip designs and IP (intellectual property) from one generation of semiconductor manufacturing process to another via trained AI algorithms.

A large percentage of chip designs are iterative and often reuse existing functionality blocks across several generations. Chip companies can still offer performance improvements when they do this by moving to a smaller manufacturing process node, such as 5nm down to 3nm. Indeed, Intel’s famous tick-tock strategy involved designing a new chip for one generation and then shrinking that down to a new process technology for the next generation. The task of adapting the designs from one process node to a smaller one (or perhaps from one chip foundry to a different manufacturing process at another chip foundry) is often a long, arduous task. The Generative AI for Design Migration feature in Virtuoso Studio is designed to tremendously simplify and speed up that process by doing much of the brute force work automatically, leveraging the embedded knowledge and existing designs of the company’s 30-year history.

In a somewhat similar way, Cadence’s recently updated Allegro X AI tool claims to offer up to a 10x reduction in time required to optimize a circuit board or system design via generative AI-based functions. In particular, the typically tedious and manual task of placing and routing between components on a board can be automated with new features integrated into Allegro X AI. The new functions optimize the positioning of components on the circuit board and the pouring of metal for interconnects and routing between them, all the while analyzing and ensuring the integrity of the signal and power connections.

Both of these updated applications offer a different take on generative AI than what we’ve seen from the likes of ChatGPT and other Large Language Model (LLM)-based tools. In a way, they’re an extension of the large base of AI-powered features that we’ve seen seeping into all kinds of applications and cloud-based services for many years now—but frankly haven’t gotten that much notice or attention. What’s interesting about these new Cadence offerings is that the amount of time they can theoretically save is more in line with what ChatGPT and other similar tools can do for some of the tasks for which they are starting to be used. Admittedly, time savings for tasks is a relatively arbitrary and subjective metric, but I believe a key part of the appeal of generative AI tools is the impressive efficiency and productivity increases they can potentially enable.

Another difference and important aspect about these types of generative AI tools is that the intelligence and learning used to power them is based on the training of a significantly smaller, but much more highly specialized data set. Chip and board designs are some of the most valuable and highly protected IP available, so it’s not likely that multiple chip companies would “contribute” their designs to a training data set that other companies could theoretically benefit from. Again, in this case, Cadence can use the company’s own in-house template designs and other IP to create the data set that powers these functions. It’s a good (and early) example of the kinds of specialized models that are likely to be developed for many different kinds of applications over the next few years (or few weeks at the rate innovation has been happening recently in the generative AI field!)

Finally, though it’s still too early to be certain, it’s interesting to think about the potential social and work-related impact of specialized generative AI tools versus the more general-purpose language-based offerings. At a panel discussion with industry experts from Cadence, Arm, Meta, Cisco, and UC Berkeley that I had the pleasure of moderating at CadenceLive, this point led to some lively conversations. The general consensus was that with the types of highly specialized skills needed to do chip design, it will be essential to keep a human in the loop. This is especially the case now, given the relative immaturity of generative AI tools for EDA and the current lack of connection to text-driven models that would theoretically enable easier interactions. Longer term, however, the impact of the technology is likely to be profound and could change not only how chips are designed and who designs them but even the type of chips that are designed.

Here’s a link to the original article: https://www.linkedin.com/pulse/latest-cadence-tools-bring-generative-ai-chip-system-design-bob

Bob O’Donnell is the president and chief analyst of TECHnalysis Research, LLC a market research firm that provides strategic consulting and market research services to the technology industry and professional financial community. You can follow him on LinkedIn at Bob O’Donnell or on Twitter @bobodtech.